Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.

This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industrys first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.

[img][/img]DATE: 02-07-2014 HOTFIX VERSION: 022
CCRID PRODUCT PRODUCTLEVEL2 TITLE
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192358 ALLEGROEDITOR PADSIN Padin does not translate some copper shapes
222141 ALLEGROEDITOR PADSIN PADSIN: Extra shapes are created when importing PADS design
274314 ALLEGROEDITOR PADSIN PADin boundary defined for flooded area be translated DYN
413919 ALLEGROEDITOR PADSIN padsin cannot import width of refdes.
609053 ALLEGROEDITOR PADSIN Mils to oversize of pads in did not work correctly for MM data.
666214 CONCEPTHDL OTHER Option to increase Line thickness in publishpdf utility
738482 ALLEGROEDITOR GRAPHICS Export image creates black image with Nvidia GeForce 8400M GS Graphics card
982950 CONCEPTHDL OTHER change the mouse button for the stroke to have same function with in pcb editor
1020886 SIPLAYOUT LEFDEFIF a quicker way to promote die pins (by importing macropin list)
1032678 CIS VIEWDATABASEPA View Database Part gives incorrect result in complex design with variants.
1033864 ALLEGROEDITOR PADSIN padsin doesnot translates teardrops present in design
1054862 CONCEPTHDL OTHER Option to increase Line thickness in publishpdf utility
1055252 FSP PROCESS Add a synthesis option to target a group to contiguous or consecutive banks
1100772 CONSTRAINTMGR OTHER In Constraint Manager > DRC > Spacing the Show Element DRC totals are wrong.
1135020 CIS DESIGNVARIANT Variant list is showing wrong results for hierarchical designs
1138951 SIPLAYOUT DIEABSTRACTIF Fix die abstract r/w to properly support pinnumbers on ports
1140042 CONSTRAINTMGR OTHER DiffPair lengths and analysis are lost after closing and opening Constraint Manager.
1143662 ALLEGROEDITOR INTERACTIV Enhancement Request for RMB - Snap Pick to options increased to include Pin edge
1147961 PSPICE SIMULATOR Simulation produces no output data
1150874 ALLEGROEDITOR PADSIN Dimensions in PADS are not translated correctly during padsin translation
1154184 CONSTRAINTMGR CONCEPTHDL Difference in the way topology is extracted in 16.3 versus 16.6
1154770 CAPTURE PROPERTYEDITOR Variant Name property doesn``t show value in Variant View mode
1158350 CONCEPTHDL CORE Need a warning Message while importing a 16.3 sub-design in a 16.6 Design
1162347 ALLEGROEDITOR EDITETCH Enh- Allow new option in Move command such that it allows stretching etch using only 45/90 degree segments directly
1165553 ALLEGROEDITOR INTERACTIV Subclass list invoked from the status window does not represent correct colors.
1168079 FSP MODELEDITOR Clicking OK or Save As in rules editor allows user to overwrite the master with no warning
1172043 SCM OTHER : in pin name causes SCM to crash
1172207 CAPTURE STABILITY Capture crash while adding new part from Spreadsheet
1172743 ADW TDA Allowed character set for the check-in comments is too limited
1174099 SIPLAYOUT WIREBOND Option to reconnect wire based on ?pin name? in the Wire Bond Replace
1177672 APD IMPORTDATA Netlist-in wizard didn?t provide detail information about what columns have been ignored by import process
1177714 CONCEPTHDL RFLAYOUTDRIVEN RF component``s LOCATION property can not be set to invisible
1177820 CONSTRAINTMGR INTERACTIV Done the Allegro command when attempting to launch CM
1178586 ALLEGROEDITOR EDITSHAPE Number of digits displayed after the decimal point of Shape Creation function does not match the Accuracy of BRD
1179688 PSPICE STABILITY pspice crash for particular HOME variable vlaue
1179827 SIPLAYOUT OTHER SiP Layout - Spreadsheet to Symbol export - enable field to add Keywords for data fields to excell cells
1179879 SIPLAYOUT STREAMIF Data file corrupt when exporting Stream data from SiP database.
1180164 F2B BOM BOM csv data format converts to excel formats
1180477 ALLEGROEDITOR INTERFACES IPC-356 output is listing a duplicate location in the comment section
1180932 SIPLAYOUT OTHER SiP Layout - Symbol to Spreadsheet add option for writing to existing spreadsheet
1181377 ALLEGROEDITOR INTERACTIV Pick Releative does not work correctly with RMB-Move Vertex
1181516 ALLEGROEDITOR DRCCONSTR Getting a Thru Pin to Route Keepout Spacing when there should not be one.
1181739 GRE CORE Running Plan > Spatial crashes GRE
1181935 ALLEGROEDITOR DATABASE Enh. Property that allows internal C-C DRC errors
1182185 SIPLAYOUT OTHER SiP Layout - Import symbol spreadsheet - suppress Family for the font in the XML spreadsheet
1182566 SIPLAYOUT OTHER SiP Layout - Spreadsheet to symbol - Enhance ability of spreadsheet exchange to allow for a portion of a full pin map
1182599 CONSTRAINTMGR DATABASE CM Prop Delay Actuals do not update after Z Axis option is turned ON or OFF and Analyze is run.
1182892 CAPTURE SCHEMATICEDITOR Pspice marker rotation before placement
1183682 ALLEGROEDITOR DRCCONSTR Implement NodrcSymPinSoldermask NodrcSymPinPastemask to symbol level
1185445 SIPLAYOUT DIEABSTRACTIF Die abstract export needs to be able to select xda file type when browsing
1185932 ALLEGROEDITOR SHAPE Soldermask in solder mask void DRC
1185946 CONCEPTHDL CORE Ericsson perfomance testing report 5 sept 2013
1187213 FLOWS PROJMGR Unable to lock the directive: backannotateforward
1187444 ALLEGROEDITOR DRCCONSTR With this design Database check prompts error SPMHGE-47: Error in call to batch DRC
1187597 ALLEGROEDITOR DRCCONSTR No Package to Package Spacing DRC error, when symbol overlap sideways at 45 degree.
1187723 FSP PROCESS Synthesis can fail depending on component placement
1188164 SIPLAYOUT OTHER SiP Layout - Spreadsheet interfaces Import Export and Add Component - include Keyword for NETGROUP
1188245 CONCEPTHDL CORE INFO(SPCOCN-2055): You cannot run the CHANGE command in a read only schematic
1190927 CONCEPTHDL CORE Check sheet does not report shorted signal/power nets if power symbol is connected to a pin
1191497 ALLEGROEDITOR INTERACTIV ENH: Adding names to the text block parameters numbers
1192005 SIPLAYOUT IMPORTDATA Import SPD2 is missing 1 smart metal shape from file
1192204 ALLEGROEDITOR EXTRACT Need ability to extract vias that are labeled as microvia
1193063 ALLEGROEDITOR MANUFACT TestPrep log displays Pin is not accessible from bottom. The component is through hole.
1193418 ALLEGROEDITOR GRAPHICS 3D Viewer cant export image in both SPB166S015 and SPB165S047
1194305 SIPLAYOUT EXPORTDATA export package overlay creates file with no package info
1194418 APD IMPORTDATA issue when do File->import->netlist-in wizard
1195279 F2B PACKAGERXL Ptf files are not being read when packaging with Cache
1195374 ALLEGROEDITOR INTERACTIV Modules are not showing up in Tools > Module reports
1196603 SIPLAYOUT EXPORTDATA Change form for Write Package Overlay... to better support longer lists of routing layers
1197302 CONSTRAINTMGR UIFORMS Inconsistancy in selection of object for Spacing Constraint Worksheet
1197399 CAPTURE OTHER Draw toolbar disappears when using Print Preview
1197543 ADW TDA TDO does not correctly show deleted pages
1198033 CONCEPTHDL CORE Signals do not get highlighted when Show Physical Net Name is option enabled
1198468 ALLEGROEDITOR GRAPHICS 3Dstep model does not show the correct view in 3DViewer when symbols have multiple placebounds.
1198617 CIS GENBOM Mech parts are showing with Part reference in CIS BOM
1199764 ALLEGROEDITOR SHAPE Allegro crashes when trying to delete small island on POWER layer.
1200232 ALLEGROEDITOR INTERACTIV Moving all items including board outline which is made of lines does not move the board outline in General Edit Mode.
1200748 ALLEGROEDITOR INTERACTIV Additional pin edge vertex object to snap pick
1201056 ALLEGROEDITOR DATABASE Unsupported functionality strip design creates a .SAV file
1201638 CIS PARTMANAGER Part retains previous linking inside the subgroup
1201834 ALLEGROEDITOR PLOTTING Bug: Import Logo command changes resulting imported object
1202406 SIPLAYOUT OTHER enable the dynamic display of component pin names for co-design dies in Sip Layout
1202431 CONCEPTHDL PDF The publishpdf -variant option should have a no graphics option
1202717 ALLEGROEDITOR DATABASE About Warning(SPMHA1-108):Illegal line segment ... end points.
1203459 CONSTRAINTMGR INTERACTIV Object Report has no mechanism to output information for a specific design.
1204544 F2B DESIGNVARI Variant Editor does not warn on save if no write permissions are on the file
1205500 FSP CONSTRAINTS MAPP FSP FPGA port mapping VHDL syntax
1205952 ALLEGROEDITOR GRAPHICS Step Model for Mechanical Part is visible in 3D viewer only when Etch Top Subclass is enabled
1206103 SIPLAYOUT ICIOEDITING add port name property to pins, and add Skill access I/O driver cell data
1206546 CAPTURE ANNOTATE User assigned refdes are resetting when ?Annotation type? is set to ?Left-Right? or ?Top-Bottom?
1206561 ALLEGROEDITOR GRAPHICS Not all mechanical symbols made with Step files are displayed in the 3D View
1207125 SIGINTEGRITY ASSIGNTOPOLOGY ECSet mapping wrong for 2 bit in a 4bit bus
1207386 CAPTURE GENERATEPART Altera pin file not generating the part properly
1207629 CAPTURE TCLINTERFACE Bug: GetMACAddresses tcl command not working
1207994 CAPTURE TCLINTERFACE TCL pdf export in 16.6 fills DOT type pins with black color
1208017 F2B DESIGNVARI sch name is not same when updating Schematic View while backannotating Variant
1209363 ALLEGROEDITOR INTERFACES When placing pins using the polar command the tool returns 4500.00 for 45 degrees.
1209769 CONCEPTHDL CORE Top DCF gate information missing
1210194 CONCEPTHDL CONSTRAINTMGR HDL crashes with Edit Via List dialog box
1210442 CONCEPTHDL INFRA Save design gives ERROR(SPCOCN-1995): Non synchronized constraint property found in schematic page
1210685 ASIPI GUI User can``t edit padstack in PowerDC-lite
1210744 SIGINTEGRITY SIGWAVE SigWave: FFT Mode Display unit seems not to be correct
1210829 CAPTURE NETLISTVERILOG Shorted port is missing from verilog file
1210850 CONCEPTHDL CORE DE-HDL backannotation crashing after instantiating specific cell from Ericsson BPc Library
1211620 ADW COMPONENTBROWSE Component Browser Performance
1212102 ALLEGROEDITOR INTERACTIV Shape edit boundary adds arc mirrored to the highlighted preview.
1213294 CONCEPTHDL SECTION DE-HDL windows mode multiple section fails to section first contactor pin from column of individual pins
1213402 APD DATABASE The old ix 0 0 fix is now causing the features to lose nets entirely.
1213694 ALLEGROEDITOR PARTITION Via connected to Dummy Net pin in Partition gets connected to shape on the board after importing partition
1214247 CONSTRAINTMGR UIFORMS Selecting the All folder in Spacing Constraints in CM does not automatically select the first column for editing
1214320 SIGINTEGRITY SIGNOISE signoise command with -L and -k option
1214433 CONCEPTHDL CORE Genview does not update sym1 with ports added to the schematic
1214909 ALLEGROEDITOR NC NC Drill Legend show extra rows for drills
1214916 SIPLAYOUT OTHER package design integrity check for via-pin alignment with fix enabled hangs
1215954 SIGINTEGRITY SIMULATION Cycle.msm does not exist error when simulating extracted net
1216328 CAPTURE STABILITY Capture crash
1216993 ALLEGROEDITOR DRCTIMINGCHK Allegro crash on SPB16.50.049
1217450 F2B BOM ERROR 233: Output file path does not exist
1217612 ALLEGROEDITOR INTERACTIV Replace padstack will not replace padstacks that have multiple alphabetic characters in the pin name - AB21-AB37
1217823 ALLEGROEDITOR INTERACTIV Compose shape fails with SPMHIS-473
1217887 ALLEGROEDITOR INTERFACES An undo option to be made available in the STEP Package Mapping window
1218665 ALLEGROEDITOR INTERFACES In step viewer, the bottom side parts are placed above the pcb board surface
1219053 PSPICE PROBE PSpice crash with the attached Design
1219067 ALLEGROEDITOR EDITETCH dynamic fillets behavior is unstable
1219095 ALLEGROEDITOR MANUFACT Design Cross section chart is tapered for two layer board
1219126 ALLEGROEDITOR SKILL Skill issue with axlRefreshSymbol()
1220701 ALLEGROEDITOR INTERACTIV View > Windows > Worldview (showhide view command) fails with command not found
1221057 ALLEGROEDITOR REPORTS Units in Cross section report for spacing is not synced with the design
1221139 ALLEGROEDITOR EDITETCH Delay tune is not tuning differential pair
1221157 SIPLAYOUT IMPORTDATA import spd2/na2 file is not importing data correctly into sip
1221163 SIGINTEGRITY GEOMETRYEXTRACT Simulation aborts with severe convergence issue when coupled vias is enabled.
1221416 ALLEGROEDITOR DATABASE strip design for function type
1221931 ALLEGROEDITOR DATABASE Fatal software error when embedding component
1222105 CONCEPTHDL CORE Moving Pins around the edge of a Block causes the text of the pin to change its text size.
1222124 APD DATABASE Same Net DRC``s exhibiting inconsistent behavior.
1222272 SIGEXPLORER EXTRACTTOP Cannot extract net or open SigXplorer after selecting a netgroup
1222329 ALLEGROEDITOR SHAPE STEP-Model Symbol which has place bound bottom is on Top
1223183 SIPLAYOUT BGAGENERATOR Getting an incorrect error message when using the BGA generator with a long BGA name.
1223662 ALLEGROEDITOR REFRESH Allegro crashes when trying to refresh symbol
1223932 CONCEPTHDL CORE DEHDL block desend does not find 1st page if its not page1
1223940 CONSTRAINTMGR UIFORMS Unable to change CLOCK name in Setup/Hold Worksheet under Timing in CM.
1224127 SIGINTEGRITY IRDROP Is the old static IRDrop in 16.6 officially supported?
1225492 PCBLIBRARIAN CORE PDV expand vector pins resizes symbol outline to maximum height again
1225546 CONSTRAINTMGR ECSAPPLY nets where the referenced ECS maps correctly in constraints manager for front end but not in back end
1226405 ALLEGROEDITOR INTERFACES File > Export > IDF ask for filter config file eventhough it is created in same session and stored in parent folder
1226448 PDNANALYSIS PCBSTATICIRDROP License failure about PDN Analysis with XL and GXL
1228721 SIPLAYOUT OTHER File Export Netlist Spreadsheet enhance sort to be a natural method per Jedec according to customer

A hot fix is a software maintenance package containing a small number of code fixes, designed to fix a small number of critical problems. A hot fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack.

Each successive Fix Pack is comprehensive and contains the material from the earlier Fix Packs for that Release, as well as all Interim Fixes made available since the previous Fix Pack or full Release. In other words, when multiple Fix Packs are available, you would not need to apply Fix Pack 1 before applying Fix Pack 2.

About Cadence Design Systems, Inc.

Cadence enables global electronic design innovation and plays an essential role in the creation of today``s integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.


Name: Cadence SPB OrCAD
Version: (32bit) 16.60.022 Hotfix
Home: www.cadence.com
Interface: english
System Requirements: Cadence SPB OrCAD 16.60.000 - 16.60.021
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